Han-Wen Hu, Demin Liu, Yi-Chieh Tsai, and Kuan-Neng Chen, and Shu-Chiao Kuo, “Bonding element and method for manufacturing the same,” U.S. Patent 11,621,641, filed on Sep. 17, 2021, Issue Date: Apr. 4, 2023.
Min-Fong Shu, Yi-Hsiu Tseng, Kuan-Neng Chen, and Shu-Chiao Kuo, “Bonding structure for semiconductor package and method of manufacturing the same,” U.S. Patent 9,984,993, filed on Oct. 14, 2016, Issue Date: May. 29, 2018.
Kuan-Neng Chen, Wei-Chung Lo, and Cheng-Ta Ko, “Bonding structure and method of fabricating the same,” U.S. Patent 9,931,813, filed on May 6, 2010, Issue Date: Apr. 3, 2018.
Min-Fong Shu, Yi-Hsiu Tseng, Kuan-Neng Chen, and Shu-Chiao Kuo, “Sloped Bonding Structure for Semiconductor Package,” U.S. Patent 9,496,238, filed on Feb. 13, 2015, Issue Date: Nov. 15, 2016.
Wen-Wei Shen, Kuan-Neng Chen, and Cheng-Ta Ko, “Semiconductor Device, Manufacturing Method and Stacking Structure Thereof,” U.S. Patent 9,373,564, filed on Mar. 6, 2015, Issue Date: Jun. 21, 2016.
Kuo-Hua Chen, Tzu-Hua Lin, Kuan-Neng Chen, and Yan-Pin Huang, “Semiconductor Bonding Structure,” U.S. Patent 9,196,595, filed on Feb. 27, 2014, Issue Date: Nov. 24, 2015.
Kuan-Neng Chen, Yao-Jen Chang, “Submicron Connection Layer and Method for Using The Same to Connect Wafers”, U.S. Patent 8,951,837, filed on Sep. 6, 2012, Issue Date: Feb. 10, 2015.
Kuan-Neng Chen, Bruce K. Furman, Sampath Purushothaman, David L. Rath, Anna W. Topol, and Cornelia K. Tsang, “Bonding of Substrates Including Metal-Dielectric Patterns with Metal Raised above Dielectric,” U.S. Patent 8,927,087, filed on Sep. 17, 2013, Issue Date: Jan. 6, 2015.
Phaedon Avouris, Kuan-Neng Chen, Damon Farmer, and Yu-Ming Lin, “Graphene Channel-Based Devices and Methods for Fabrication Thereof”, U.S. Patent 8,900,918, filed on May 2, 2013, Issue Date: Dec. 2, 2014.
Phaedon Avouris, Kuan-Neng Chen, Damon Farmer, and Yu-Ming Lin, “Graphene Channel-Based Devices and Methods for Fabrication Thereof,” U.S. Patent 8,878,193, filed on May 2, 2013, Issue Date: Nov. 4, 2014.
Chi-Chung Chang, Chih-Hung Chiu, Yen-Chi Chen, Kuan-Neng Chen, Jian-Yu Shih, “Through Silicon Via-Based Oscillator Wafer-level-package Structure and Method for Fabricating the Same,” U.S. Patent 8,766,734, filed on Jun. 22, 2012, Issue Date: Jul. 1, 2014.
Phaedon Avouris, Kuan-Neng Chen, Damon Farmer, and Yu-Ming Lin, “Graphene Channel-Based Devices and Methods for Fabrication Thereof”, U.S. Patent 8,698,165, filed on May 2, 2013, Issued Date: Apr. 15, 2014.
Kuan-Neng Chen, Cheng-Ta Ko, and Wei-Chung Lo, “Heterostructure Containing IC and LED and Method for Fabricating the Same,” U.S. Patent 8,679,891, filed on Jan 2, 2014, Issue Date: Mar. 25, 2014.
Kuan-Neng Chen, Ming-Fang Lai, and Hung-Ming Chen, “Integrated Circuit Device”, U.S. Patent 8,653,641, filed on Sep. 13, 2012, Issue Date: Feb. 18, 2014.
Kuan-Neng Chen, Bruce K. Furman, Sampath Purushothaman, David L. Rath, Anna W. Topol, and Cornelia K. Tsang, “Bonding of Substrates Including Metal-Dielectric Patterns with Metal Raised above Dielectric and Structures So Formed,” U.S. Patent 8,617,689, filed on Apr. 10, 2012, Issue Date: Dec. 31, 2013.
Kuan-Neng Chen, and Fei Liu, “Precise-aligned lock-and-key bonding structures”, U.S. Patent 8,603,862, filed on May 14, 2010, Issue Date: Dec. 10, 2013.
Kuan-Neng Chen, Shih-Wei Li, “Stacking Error Measurement with Electrical Test Structure Applying 3D-ICs Bonding Technology”, U.S. Patent 8,546,952, filed on Nov. 11, 2011, Issue Date: Oct. 1, 2013.
Kuan-Neng Chen, Cheng-Ta Ko, and Wei-Chung Lo, “Heterostructure Containing IC and LED and Method For Fabricating the Same,“ U.S. Patent 8,536,613, filed on Sep 2, 2011, Issue Date: Sep. 17, 2013.
Kuan-Neng Chen, and Sampath Purushothaman, “Programmable via devices”, U.S. Patent 8,525,144, filed on Jul. 29, 2009, Issue Date: Sep. 3, 2013.
Kuan-Neng Chen, Sheng-Yao Hsu, “Bonding Method for Three-Dimensional Integrated Circuit and Three-Dimensional Integrated Circuit Thereof”, U.S. Patent 8,508,041, filed on Dec. 14, 2011, Issued Date: Aug. 13, 2013.
Phaedon Avouris, Kuan-Neng Chen, and Yu-Ming Lin, “Method to fabricate high performance carbon nanotube transistor integrated circuits by 3D integration technology”, U.S. Patent 8,455,297, filed on July 7, 2010, Issued Date: Jun. 4, 2013.
Phaedon Avouris, Kuan-Neng Chen, Damon Farmer, and Yu-Ming Lin, “Graphene Channel-Based Devices and Methods for Fabrication Thereof”, U.S. Patent 8,445,320, filed on May 20, 2010, Issued Date: May 21, 2013.
Solomon Assefa, Kuan-Neng Chen, Yurii A. Vlasov, and Steven J. Koester, “Three-dimensional integrated circuits and techniques for fabrication thereof”, U.S. Patent 8,426,921, filed on Feb 1, 2011, Issued Date: Apr. 23, 2013.
Bruce G. Elmegreen, Lia Krusin-Elbaum, Glenn J. Martna, Xiao Hu Liu, Dennis M. Newns, and Kuan-Neng Chen, “Coupling piezoelectric material generated stresses to devices formed in integrated circuits”, U.S. Patent 8,405,279, filed on Jun. 26, 2012, Issued Date: Mar. 26, 2013.
Kuan-Neng Chen, and Sampath Purushothaman, “Programmable via devices”, U.S. Patent 8,389,967, filed on Oct. 18, 2007, Issued Date: Mar. 5, 2013.
Bruce G. Elmegreen, Lia Krusin-Elbaum, Glenn J. Martna, Xiao Hu Liu, Dennis M. Newns, and Kuan-Neng Chen, “Coupling piezoelectric material generated stresses to devices formed in integrated circuits”, U.S. Patent 8,247,947, filed on Dec. 7, 2009, Issued Date: Aug. 21, 2012.
Kuan-Neng Chen, Lia Krusn-Elbaum, Dennis Newns, and Sampath Purushothaman, “Programmable via devices in back of line level”, U.S. Patent 8,243,507, filed on May 13, 2011, Issue Date: Aug. 21, 2012.
Kuan-Neng Chen, Bruce K. Furman, Sampath Purushothaman, David L. Rath, Anna W. Topol, and Cornelia K. Tsang, “Bonding of Substrates Including Metal-Dielectric Patterns with Metal Raised above Dielectric,” U.S. Patent 8,241,995, filed on Sep. 18, 2006, Issue Date: Aug. 14, 2012.
Kuan-Neng Chen, John Arnold and Niranja Ruiz, “Methods of forming tubular objects”, U.S. Patent 8,168,542, filed on Jan 3, 2008, Issue Date: May 1, 2012.
Solomon Assefa, Kuan-Neng Chen, Yurii A. Vlasov, and Steven J. Koester, “Techniques for three-dimensional circuit integration”, U.S. Patent 8,129,811, filed on Apr 16, 2011, Issue Date: Dec 13, 2011.
Kuan-Neng Chen, and Fei Liu, “Scalable transfer-join bonding lock-and-key structures”, U.S. Patent 8,076,177, filed on May 14, 2010, Issue Date: Dec 13, 2011.
Kuan-Neng Chen, and Lia Krusn-Elbaum, “Four-terminal reconfigurable devices”, U.S. Patent 8,053,752, filed on Jan. 8 2011, Issue Date: Nov 8, 2011.
Kuan-Neng Chen, John Arnold, and Niranjana Ruiz, “Methods of forming features in integrated circuits”, U.S. Patent 8,012,811, Filing Date: Jan 3, 2008, Issue Date: Sep 6, 2011.
Kuan-Neng Chen, “CMOS-process-compatible programmable via device”, U.S. Patent 7,982,203, Filing Date: Feb 1, 2010, Issue Date: Jul 19, 2011.
Kuan-Neng Chen, Lia Krusn-Elbaum, Dennis Newns, and Sampath Purushothaman, “Programmable via devices with air gap isolation”, U.S. Patent 7,977,203, Filing Date: Aug 20, 2009, Issue Date: Jul 12, 2011.
Kuan-Neng Chen, Lia Krusn-Elbaum, Dennis Newns, and Sampath Purushothaman, “Programmable via devices in back of line level”, U.S. Patent 7,969,770, Filing Date: Aug. 3, 2007, Issue Date: Jun. 28, 2011.
Solomon Assefa, Kuan-Neng Chen, Yurii A. Vlasov, and Steven J. Koester, “Techniques for three-dimensional circuit integration”, U.S. Patent 7,955,887, Filing Date: Jun. 3, 2008, Issue Date: Jun. 7, 2011.
Matthew J. Breitwisch and Kuan-Neng Chen, “Wafer bonded access device for multi-layer phase change memory using lock-and-key alignment”, U.S. Patent 7,927,911, Filing Date: Aug. 28, 2009, Issue Date: Apr. 19, 2011.
Solomon Assefa, Kuan-Neng Chen, Yurii A. Vlasov, and Steven J. Koester, “Three-dimensional integrated circuits and techniques for fabrication thereof”, U.S. Patent 7,897,428, Filing Date: Jun 3, 2008, Issue Date: Mar 1, 2011.
Kuan-Neng Chen, Lia Krusin-Elbaum, Chung H. Lam, and Albert M. Young, “Programmable Via Structure and Method of Fabricating Same”, U.S. Patent 7,888,164, Filing Date: Aug 8, 2009, Issue Date: Feb 15, 2011.
Kuan-Neng Chen, and Lia Krusn-Elbaum, “Four-terminal reconfigurable devices”, U.S. Patent 7,880,157, Filing Date: Aug 19, 2009, Issue Date: Feb 1, 2011.
Kuan-Neng Chen, “CMOS-process-compatible programmable via device”, U.S. Patent 7,811,933, Filing Date: Feb 1, 2010, Issue Date: Oct 12, 2010.
Kuan-Neng Chen, Bruce K. Furman, Edmund J. Sprogis, Anna W. Topol, Cornelia K. Tsang, Matthew R. Wordeman, and Albert M. Young, “Hermetic Seal and Reliable Bonding Structures for 3D Applications”, U.S. Patent 7,786,596, Filing Date: Feb 27, 2008, Issue Date: Aug 31, 2010.
Kuan-Neng Chen, and Lia Krusn-Elbaum, “Four-terminal reconfigurable devices”, U.S. Patent 7,772,582, Filing Date: July 11, 2007, Issue Date: Aug 10, 2010.
Kuan-Neng Chen, “CMOS-process-compatible programmable via device”, U.S. Patent 7,687,309, Filing Date: Jun 28, 2007, Issue Date: Mar 30, 2010.
Kuan-Neng Chen, Bruce K. Furman, Edmund J. Sprogis, Anna W. Topol, Cornelia K. Tsang, Matthew R. Wordeman, and Albert M. Young, “Hermetic Seal and Reliable Bonding Structures for 3D Applications”, U.S. Patent 7,683,478, Filing Date: Feb 6, 2008, Issue Date: Mar 23, 2010.
Kuan-Neng Chen, Dennis Newns, Sampath Purushothaman, and Lia Krusn-Elbaum, “Programmable via devices with air gap isolation”, U.S. Patent 7,659,534, Filing Date: Aug 3, 2007, Issue Date: Feb 9, 2010.
Kuan-Neng Chen, Lia Krusin-Elbaum, Chung H. Lam, and Albert M. Young, “Programmable Via Structure and Method of Fabricating Same”, U.S. Patent 7,652,278, Filing Date: Dec 19, 2006, Issue Date: Jan 26, 2010.
Kuang-Neng Chen, Bruce G. Elmegreen, Doek-Kee Kim, Chandrasekharan Kothandaraman, Lia Krusin-Elbaum, Chung H. Lam, Dennis Newns, Byeongju Park, and Sampath Purushothaman, “Programmable fuse/non-volatile memory structures in BEOL regions using externally heated phase change material”, U.S. Patent 7,633,079, Filing Date: Sep. 6, 2007, Issue Date: Dec. 15, 2009.
Kuan-Neng Chen, and Chung H. Lam, “Switch array of circuit and system using programmable via structures with phase change materials”, U.S. Patent 7,608,851, Filing Date: May 8, 2007, Issue Date: Oct 27, 2009.
Kuan-Neng Chen, and Chung H. Lam, “Four-terminal programmable via-containing structure and method of fabricating same”, U.S. Patent 7,579,616, Filing Date: Apr 10, 2007, Issue Date: Aug 25, 2009.
Rafael Reif, Kuan-Neng Chen, Chuan Seng Tan, and Andy Fan, “Method of Forming a Multi-Layer Semiconductor Structure Incorporating a Processing Handle Member,” U.S. Patent 7,307,003, Filing Date: Dec 30, 2003, Issue Date: Dec 11, 2007.
Japan
陳冠能, 李世偉, “三次元集積回路”, 特許第5624081號, filed on May 22, 2012, Issue Date: Oct 3, 2014.
Korea
陳冠能, 徐聖堯, “三維積體電路之接合方法及其三維積體電路”, Korea Patent No. 10-1384131, filed on Feb. 3, 2012, Issue Date: Apr. 4, 2014.
陳冠能, 李世偉, “Stacking Error Measurement with Electrical Test Structure Applying 3D-ICs Bonding Technology”, Korea Patent No. 10-1373267, filed on Nov. 10, 2011, Issue Date: Mar. 5, 201
Kuan-Neng Chen, Cheng-Ta Ko, and Wei-Chung Lo, “Heterostructure Containing IC and LED and Method For Fabricating the Same,“ Korean Patent 10-1259308, filed on Aug 31, 2011, Issue Date: Apr. 23, 2013.
Kuan-Neng Chen, Ming-Fang Lai, and Hung-Ming Chen, “ESD Protection Structure for 3D IC”, Korea Patent 10-1227872, filed on Apr. 20, 2011, Issued Date: Jan. 24, 2013.
