3D IC Integration & Novel Applications
Novel Low Warpage Hyper RDL (HRDL) Interposer
- Multiple-layer RDL stacking without CMP process
- Reduce warpage issue
- Low-temperature hybrid bonding technology
- Reliability test: TCT, u-HAST
Novel Material – Polyimide
- Optimization of lithography process
- Evaluation and improvement of adhesion
- Reliability test: chemical resist test, TCT, u-HAST
- Design and verification of electrical characteristics
- BEOL location-controlled grain (LCG) technique
- Controlled thermal budgets
- Monolithic fabricated single-crystal Si islands (SCI)
- 40 nm FinFETs in Si islands with excellent electrical performance
Wafer-level Bumpless Through-Silicon-Via (TSV)
- Wafer-level polymer bonding technology
- Design and fabrication of bumpless TSV structure
- Plasma via bottom cleaning technique
- Reliability test: EM test, TCT, u-HAST.
- Novel lumped circuit model for HBM applications
Scroll to top
