ISSCC/IEDM/VLSI
20
Journal
140
Conference
237
Patent
87
Books
10
- Bo-Jheng Shih, Shie-Ping Chang, Ting-Yu Chen, Zih-Yang Chen, Po-Jung Sung, Nein-Chih Lin, Chih-Chao Yang, Po-Tsang Huang, Huang-Chung Cheng, Ming-Yang Li, Iuliana P. Radu, and Kuan-Neng Chen, “Precise Alignment in Ultra-Thin (< 1 µm) Interlayer Wafer-Level Active Device Transfer with SOI Temporary Bonding,” 2024 International Electron Devices Meeting (IEDM), San Francisco CA, Dec. 7-11, 2024.
- Yu-Lun Liu, Chien-Kang Hsiung, Chun-Ta Li, Tzu-Han Sun, Yu-Tao Yang, Wen-Tzu Tsai, MuPing Hsu, and Kuan-Neng Chen, “Hyper RDL (HRDL) Interposer by Layer Transfer Technology for 3D IC and Advanced Packaging,” 2024 International Electron Devices Meeting (IEDM), San Francisco CA, Dec. 7-11, 2024.
- Bo-Jheng Shih, Yu-Ming Pan, Hao-Tung Chung, Chieh-Ling Lee, I-Chun Hsieh, Nein-Chih Lin, Chih-Chao Yang, Po-Tsang Huang, Hung-Ming Chen, Chiao-Yen Wang, Huan-Yu Chiu, Huang-Chung Cheng, Chang-Hong Shen, Wen-Fa Wu, Tuo-Hung Hou, Kuan-Neng Chen, and Chenming Hu, “3DIC with Stacked FinFET, Inter-level Metal, and Field-Size (25x33mm2) Single-Crystalline Si on SiO2 by Elevated-Epi,” 2024 Symposia on VLSI Technology and Circuits, Honolulu, HI, Jun. 16-20, 2024.
- Wei Lu, Jie Zhang, Yi-Hui We, Hsu-Ming Hsiao, Sih-Han Li, Chao-Kai Hsu, Chih-Cheng Hsiao, Feng-Hsiang Lo, Shyh-Shyuan Sheu, Chin-Hung Wang, Wei-Chung Lo, Shih-Chieh Chang, Hung-Ming Chen, Kuan-Neng Chen, and Po-Tsang Huang, “Scalable Embedded Multi-Die Active Bridge(S-EMAB) Chips with Integrated LDOs for Low-Cost Programmable 2.5D/3.5D Packaging Technology,” 2024 Symposia on VLSI Technology and Circuits, Honolulu, HI, Jun. 16-20, 2024.
- Zhong-Jie Hong, Demin Liu, Shu-Ting Hsieh, Han-Wen Hu, Ming-Wei Weng, Chih-I Cho, Jui-Han Liu, and Kuan-Neng Chen, “Room Temperature Cu-Cu Direct Bonding Using Wetting/Passivation Scheme for 3D Integration and Packaging,” 2022 Symposia on VLSI Technology and Circuits, Honolulu, HI, 12-17, 2022.
- Jie Zhang, Wei Lu, Po-Tsang Huang, Sih-Han Li, Tsung-Yi Hung, Shih-Hsien Wu, Ming-Ji Dai, I-Shan Chung, Wen-Chao Chen, Chin-Hung Wang, Shyh-Shyuan Sheu, Hung-Ming Chen, Kuan-Neng Chen, Wei-Chung Lo, and Chih-I Wu, “An Embedded Multi-Die Active Bridge (EMAB) Chip for Rapid-Prototype Programmable 2.5D/3D Packaging Technology,” 2022 Symposia on VLSI Technology and Circuits, Honolulu, HI, 12-17, 2022.
- Hao-Tung Chung, Bo-Jheng Shih, Chih-Chao Yang, Nei-Chih Lin, Po-Tsang Huang, Yun-Ping Lan, Kuan-Fu Lai, Wan-Ting Hsu, Yu-Ming Pan, Zhong-Jie Hong, Han-Wen Hu, Huang-Chung Cheng, Chang-Hong Shen, Jia-Min Shieh, Da-Chiang Chang, Wen-Kuan Yeh, Kuan-Neng Chen, and Chenming Hu, “Ge Single-Crystal-Island (Ge-SCI) Technique and BEOL Ge FinFET Switch Arrays on Top of Si Circuits for Monolithic 3D Voltage Regulators,” 2021 International Electron Devices Meeting (IEDM), Virtual Conference, 11-15, 2021.
- Po-Tsang Huang, Yu-Wei Liu, Kuan-Fu Lai, Yun-Ping Lan, Tzung-Han Tsai, Bo-Jheng Shih, Ping-Yi Hsieh, Chih-Chao Yang, Chang-Hong Shen, Jia-Min Shieh, Da-Chiang Chang, Kuan-Neng Chen, Wen-Kuan Yeh, and Chenming Hu, “Crystal-Orientation-Tolerant Voltage Regulator using Monolithic 3D BEOL FinFETs in Single-Crystal Islands for On-Chip Power Delivery Network,” 2020 International Electron Devices Meeting (IEDM), Virtual Conference, 7-11, 2020.
- Demin Liu, Po-Chi Chen, Chien-Kang Hsiung, Shin-Yi Huang, Yan-Pin Huang, Steven Verhaverbeke, Glen Mori, and Kuan-Neng Chen, “Low Temperature Cu/SiO2 Hybrid Bonding with Metal Passivation,” 2020 Symposia on VLSI Technology and Circuits, Virtual Conference, 14-19, 2020.
- Tzu-Chieh Chou, Kai-Ming Yang, Jian-Chen Li, Ting-Yang Yu, Ying-Ting Chung, Cheng-Ta Ko, Yu-Hua Chen, Tzyy-Jang Tseng, and Kuan-Neng Chen, “Non-Planarization Cu-Cu Direct Bonding and Gang Bonding with Low Temperature and Short Duration in Ambient Atmosphere,” 2019 International Electron Devices Meeting (IEDM), San Francisco CA, Dec. 7-11, 2019.
- Ping-Yi Hsieh, Yi-Jui Chang, Pin-Jun Chen, Chun-Liang Chen, Chih-Chao Yang, Po-Tsang Huang, Yi-Jing Chen, Chih-Ming Shen, Yu-Wei Liu, Chien-Chi Huang, Ming-Chi Tai, Wei-Chung Lo, Chang-Hong Shen, Jia-Min Shieh, Da-Chiang Chang, Kuan-Neng Chen, Wen-Kuan Yeh, and Chenming Hu, “Monolithic 3D BEOL FinFET switch arrays using location-controlled-grain technique in voltage regulator with better FOM than 2D regulators”, 2019 International Electron Devices Meeting (IEDM), San Francisco CA, Dec. 7-11, 2019.
- Chih-Chao Yang, Tung-Ying Hsieh, Po-Tsang Huang, Kuan-Neng Chen, Wan-Chi Wu, Shih-Wei Chen, Chia-He Chang, Chang-Hong Shen, Jia-Min Shieh, Chenming Hu, Meng-Chyi Wu, and Wen-Kuan Yeh, “Location-controlled-grain Technique for Monolithic 3D BEOL FinFET Circuits”, 2018 International Electron Devices Meeting (IEDM), San Francisco CA, Dec. 1-5, 2018.
- Yu-Chen Hu, Chun-Pin Lin, Hsiao-Chun Chang, Yu-Tao Yang, Chi-Shi Chen, and Kuan-Neng Chen, “An Advanced 3D/2.5D Integration Packaging Approach Using Double-Self-Assembly Method with Complex Topography, and Micropin-Fin Heat Sink Interposer for Pressure Sensing System”, 2016 International Electron Devices Meeting (IEDM), San Francisco CA, Dec. 3-7, 2016.
- Yu-Chieh Huang, Yu-Chen Hu, Po-Tsang Huang, Shang-Lin Wu, Yan-Huei You, Jr-Ming Chen, Yan-Yu Huang, Hsiao-Chun Chang, Yen-Han Lin, Jeng-Ren Duann, Tzai-Wen Chiu, Wei Hwang, Ching-Te Chuang, Jin-Chern Chiou, and Kuan-Neng Chen, “Integration of Neural Sensing Microsystem with TSV-embedded Dissolvable µ-Needles Array, Biocompatible Flexible Interposer, and Neural Recording Circuits”, 2016 Symposia on VLSI Technology and Circuits, Honolulu, HI, Jun. 13-17, 2016.
- Po-Tsang Huang, Lei-Chun Chou, Shang-Lin Wu, Teng-Chieh Huang, Tang-Shuan Wang, Yu-Rou Lin, Chuan-An Cheng, Wen-Wei Shen, Kuan-Neng Chen, Jin-Chern Chiou, Ching-Te Chuang, Wei Hwang, Kuo-Hua Chen, Chi-Tsung Chiu, Ming-Hsiang Cheng, Yueh-Lung Lin, and Ho-Ming Tong, “2.5D Heterogeneously Integrated Bio-Sensing Microsystem for Multi-Channel Neural Sensing Applications,” 2014 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb 9-13, 2014.
- Chih-Wei Chang, Po-Tsang Huang, Lei-Chun Chou, Shang-Lin Wu, Shih-Wei Lee, Ching-Te Chuang, Kuan-Neng Chen, Jin-Chern Chiou, Wei Hwang, Yen-Chi Lee, Chung-Hsi Wu, Kuo-Hua Chen, Chi-Tsung Chiu, and Ho-Ming Tong,” Through-Silicon-Via Based Double-Side Integrated Microsystem for Neural Sensing Applications”, 2013 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb 13-17, 2013, pp. 102-103.
- K. N. Chen, T. M. Shaw, C. Cabral, Jr., and G. Zuo, “Reliability and structural design of a wafer-level 3D integration scheme with W TSVs based on Cu-oxide hybrid wafer bonding”, 2010 International Electron Devices Meeting (IEDM), San Francisco CA, Dec. 6-8, 2010.
- R. Yu, F. Liu, R. J. Polastre, K. N. Chen, X. H. Liu, L. Shi, E. D. Perfecto, N. R. Klymko, M. S. Chace, T. M. Shaw, D. Dimilia, E. R. Kinser, A. M. Young, S. Purushothaman, S. J. Koester and W. Haensch, “Reliability of a 300-mm-compatible 3DI technology based on hybrid Cu-adhesive wafer bonding”, 2009 Symposia on VLSI Technology and Circuits, Kyoto, Japan, Jun. 15-18, 2009.
- Liu, R. R. Yu, A. M. Young, J. P. Doyle, X. Wang, L. Shi, K. N. Chen, X. Li, D. A Dipaola, D. Brown, C. T. Ryan, J. A Hagan, K. Wong, M. Lu, X. Gu, N. Klymko, E. Perfecto, A. G. Merryman, K. Kelly, S. Purushothaman, S. J. Koester, R. Wisneieff, and W. Haensch, “A 300-mm Wafer-Level Three-Dimensional Integration Scheme Using Tungsten Through-Silicon Via and Hybrid Cu-Adhesive Bonding”, 2008 International Electron Devices Meeting (IEDM), San Francisco CA, Dec. 15-17, 2008.
- Kuan-Neng Chen, Sang Hwui Lee, Paul S. Andry, Cornelia K. Tsang, Anna W. Topol, Yu-Ming Lin, Jian-Qiang Lu, Albert M.Young, Meikei Ieong, and Wilfried Haensch, “Structure Design and Process Control for Cu Bonded Interconnects in 3D Integrated Circuits”, 2006 International Electron Devices Meeting (IEDM), pp. 367-370, San Francisco CA, Dec. 11-13, 2006.
